1. Field of the Invention
The present invention relates to a semiconductor device equipped with antifuse elements for use, for example, in an FPGA (Field Programmable Gate Array) and a method for the manufacturing the same.
2. Description of the Related Art
An antifuse element comprises a pair of conductors and a high resistive body or insulator inserted between these conductors. The antifuse element is of such an electrically programmable type that it reveals an insulating or high resistive property in an initial state (a non-programmed state) and a low resistive or conducting state in a programmed state (after the application of a predetermined voltage). The antifuse element is used in a conventional PROM, such as a fuse ROM, and, in recent years, in an FPGA, one kind of a gate array.
The gate array has the feature that it is capable of developing a desired LSI for a brief period of time by initially manufacturing a chip with basic cells arranged and making electrical connection. Since, conventionally, the electrical connection layout is prepared using, as a mask, an electrical connection pattern formed based on a computer-aided designing (CAD), there is a tendency that less number of electrical connections leads to a greater mask manufacturing cost per chip. Under this situation, a gate array called a "FPGA" has been developed, in recent years, which can make electrical connection without the need of the user's preparing a mask. In order that, for FPGA, a plurality of basic cells may be properly joined on the side of a manufacturer, two connection layer groups are arranged in a grid-like array with an insulating film placed therebetween and an opening is provided, at each grid intersection, in the insulating interlayer in which case a thin insulating film is interposed at the opening between the connection layers.
When a normal operation voltage is applied, the thin insulating film is not conducting. When, on the other hand, a voltage exceeding a predetermined level is applied, an irreversible dielectric breakdown occurs, thus causing the upper and lower connection layers to be conducted. In the semiconductor chip a device is provided which applies a predetermined voltage to the insulating film at any given intersection point. The manufacturer sells such a semiconductor chip as a packaged product. On the other hand, the user makes proper electrical connections between the two connection layers through the conduction of the insulating film by a device for applying a predetermined voltage. By so doing it is possible to achieve desired interconnection at desired intersections.
The insulating film interposed between the conductive layers in FPGA is insulated at a normal time and conducted at a desired time. Hence the name of the antifuse element having just the opposite property to an ordinary fuse element. The antifuse element in FPGA, being incorporated into a logic circuit, demands such a characteristic as not to involve a fall in the operation speed of the circuit.
The antifuse element has, for example, the following requisite characteristics that
(1) it is insulated or adequately high resistive in an initial state; PA1 (2) it is conducted with the application of a desired program voltage; PA1 (3) it, being selected at the program time, stays in a permanently adequately low resistive state after the end of the program; PA1 (4) it, being not selected at the program time, is maintained, by a normal circuit operation voltage, in a permanently insulated or highly resistive state after the end of the program; and PA1 (5) it, being in the nonconducted state, involves a small capacitive level. PA1 (a) An antifuse element in an initial state, a resistance R.sub.int &gt;1 G.OMEGA. per element. PA1 (b) A program voltage V.sub.pp &lt;20V (Under the present situation, 1.5 V.sub.dd &lt;V.sub.pp &lt;3 V.sub.dd for a normal operation voltage V.sub.dd). PA1 (c) For a programmed conductive antifuse, R.sub.on &lt;150 .OMEGA. per element. PA1 (d) For a programmed nonconductive antifuse element, a resistance R.sub.off &gt;1 G.OMEGA. per element. PA1 (e) For a nonconductive antifuse element, a capacitance C.sub.off &lt;3 fF per element. PA1 (f) At a time of a normal circuit operation, a nonconductive antifuse element maintains R.sub.off at an operation voltage V.sub.dd for 10 years. PA1 a semiconductor substrate; PA1 a first electrode formed over the semiconductor substrate and comprised of an Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the Al connection layer; PA1 an antifuse film formed on and in contact with the first electrode and formed of silicon nitride whose nitrogen/silicon atomic composition (N/Si) ratio ranges from 0.6 to 1.2; and PA1 a second electrode formed on the antifuse film and electrically connectable to the first electrode with the antifuse film formed therebetween, and comprised of the barrier metal layer serving as a barrier against the Al. PA1 forming a first electrode over-a major surface of a semiconductor substrate, the first electrode being comprised of an Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on the Al connection layer and serving as a barrier against the Al; PA1 forming an insulating film over the semiconductor substrate so as to cover the first electrode; PA1 forming an opening in the insulating film so as to partially expose the first electrode; PA1 forming an antifuse film, by a plasma CVD method, in a manner to partly cover the insulating film and contact with the barrier metal layer of the first electrode via the opening, the antifuse film being formed of silicon nitride whose nitrogen/silicon atomic composition ratio (N/Si) ranges from 0.6 to 1.2; and PA1 forming a second electrode on the antifuse film, the second electrode being formed of a barrier metal layer serving as a barrier against the Al.
The aforementioned requisite characteristics of the antifuse element are determined based on the product specification of FPGA, such as a power supply voltage (V.sub.dd), program voltage (V.sub.pp), circuit speed, allowable dissipation power and long-term reliability. Further, the product of FPGA is governed based on the specification of an ordinary gate array of the same generation and determined based on the scaling rules of CMOS-LSI.
In practice, in the generation of the power supply voltage 5V far instance, the requisite characteristics of the antifuse for FPGA are as follows:
It is very difficult in practice to realize the antifuse characteristic thus far explained. The reason for this is as will be set out below. From the stand-point of the properties of matter for instance, the insulating material film, being thicker and hence higher in its insulating property, leads to a decrease in leak current and in capacitance, while, on the other hand, the program voltage is increased and, after conduction, the resistance becomes high so that the long-term reliability of a nonconductive antifuse element is adversely affected. In view of such mutual opposite properties, it is necessary to carefully select the structure and material of the antifuse element.
The conventional antifuse is of such a type that a silicon oxide film, silicon nitride film or stacked layer of these is sandwiched between silicon and silicon or polysilicon and polysilicon (U.S. Pat. No. 4,876,220). In this structure, a resistance (ON resistance after conduction is made is as high as over 10000 .OMEGA. and the structure above is not suitable to a low resistance-demanding FPGA. At a later time, it has been found that the ON resistance can be made low when metal is used for the upper and lower electrodes for the antifuse. A proposal has been made to use a structure where amorphous silicon is sandwiched between the upper and lower electrodes at an Al/barrier metal stack layer (U.S. Pat. No. 5,100,827). The prior art device will be explained below with reference to FIG. 1. A barrier metal layer (TiW)3 is deposited on a underlying Al connection layer 2 overlying a silicon semiconductor substrate 1 and a resultant semiconductor is patterned to provide a first electrode for an antifuse element. The reason that the electrode is formed of a laminated structure of the Al layer and barrier metal layer is because the process steps are not adversely affected due to a reaction being developed between a silicide and a amorphous silicon, that is, a high resistive material, which results from the diffusion of Al in a later heat treating step. A first insulating film 4 is deposited on the electrode comprised of the Al layer 2 and barrier metal 3. An opening 5 is provided in the first insulating film 4 to partially expose the surface of the barrier metal layer 3 of the first electrode. In order that, at a subsequent step of depositing amorphous silicon, the amorphous silicon is properly formed over the exposed opening 5, the first insulating film 4 has such a film thickness as to provide an aspect ratio of 1/2 relative to the opening 5. Then a non-doped amorphous silicon 6 is deposited as a high resistive layer material on the resultant structure and patterning is effected, leaving the amorphous silicon only over the opening 5. In order to make at a low resistive level a conduction area after a programmed state, a conductive layer 7 is deposited and a barrier metal 8 is formed over the conductive layer 7. A second insulating film (plasma TEOS)9 is deposited over the barrier metal layer 8 and an opening 10 is formed in the insulating film 9 at an area above the amorphous silicon 6. An overlying Al connection layer 11 is deposited over the second insulating layer 9, followed by a patterning step. In this way, in the prior art device, an antifuse is formed between the Al connection layers using amorphous silicon as a high resistive material and a high-reliable antifuse is realized.
From the standpoint of material selection, if this material and structure are used, the ON resistance can be lowered down to about 500 .OMEGA. but it is not sufficient as the characteristic of the antifuse for FPGA. There is a possibility that, if the amorphous silicon layer is made thinner, the ON resistance will be made lower. However, a new problem arises from the fact that, if the layer above is thinned, the resistance of the antifuse at a nonconductive time is lowered. Another problem with the antifuse using the amorphous silicon as the insulating layer is that the resistivity greatly varies depending upon the-amount of hydrogen or other impurities (N. Savvides, J. Appl. Phys., 56, 2789, 1984). If, for example, the amount of hydrogen varies form 0% to 10%, the resistivity varies by six orders of magnitude and the film thickness satisfying the aforementioned characteristic (a) will vary from 1 nm to 1000 nm. In a practical process, hydrogen enters the amorphous silicon upon deposition of the insulating interlayer, for example, at low temperature, or at a post-process such as sintering, but it is difficult to control the amount of hydrogen actually entering the amorphous silicon and hence difficult to, if the amorphous silicon is used, prepare an antifuse element with the OFF resistance (characteristic (a)) stabilized.
As another prior art technique using metal for the upper and lower electrodes as disclosed, for example, U.S. Pat. No. 5,166,556, a proposal has been made to provide a structure where an insulating material, such as silicon nitride (SiNx, 0&lt;x&lt;1.4), is sandwiched between high melting point metal (titanium) layers. According to this technique, if a 30 nm-400 nm-thick nonstoichiometric amorphous silicon-based insulating layer is used, it is indicated that, with a 100M.OMEGA. OFF resistance and program voltage scalable from 3V to 40V, it is possible to provide an antifuse having an ON resistance of about 100 .OMEGA.. The technique above has the feature that the antifuse characteristic, such as the program voltage, is scalable or adjustable. This is realized by depositing the antifuse layer (insulating layer) on the surface by means of a plasma CVD method and varying the gas flow ratio. As known in the prior art, if the gas flow ratio is varied, the composition ratio of the insulating film to be deposited and hence the properties of matter vary. Taking this fact into consideration, the technique above is applied to the antifuse. (1) Since, according to the technique, not only the titanium but also other high melting point metals are used for upper and lower electrodes and connection layers, it is not possible to realize the circuit speed based on an ordinary CMOS-LSI using Al connection layers. (2) Although the composition of the nonstoichiometric silicon nitride (SiNx) is in a range 0&lt;x&lt;1.4 (this is an area all covered from the amorphous silicon to the stoichiometric silicon nitride Si.sub.3 N.sub.4), all the requisite characteristics (a) to (f) of the antifuse for FPGA are not satisfied over a whole composition range of 0&lt;x.ltoreq.1.4 from the standpoint of the dependence of various properties of matter of the silicon nitride (SiNx) upon its composition ratio (referring to a later description or see M. Takagi et. al, IEDM Technical Digest (1993)). In the case where Al is used for the electrodes and connection layers so as to realize a CMOS-LSI-based circuit speed, (3) if a higher energy is produced at the antifuse at the is program time the Al connection layer is melted/broken and the selective range of the antifuse material becomes stricter than in the case where the high melting point metal is used for the connection layers and electrodes. It is not possible to prepare an antifuse, for FPGA, over the whole composition range of 0&lt;x&lt;1.4. In the prior art manufacturing method above, it becomes difficult to control the thickness of the antifuse's insulating film at the bottom surface corner of bias from the standpoint of the problem with the step coverage of the antifuse film. It is, therefore, not possible to properly control the program voltage and OFF leak current.
In the prior art arrangement, a high-reliable antifuse element is achieved by providing the barrier metal layer 3 on the Al connection layer 2 and defining, for example, the aspect ratio of the opening where the amorphous silicon is deposited. According to the present invention, the ON resistance can be lowered to about 500 .OMEGA.. Judging from the overall point of view including a consideration on the process of antifuse element for FPGA, however, it may be said that neither the material selection nor the structural designing of the antifuse element is properly made at all times. Although the amorphous silicon is selected as an insulating material or high resistive material, it is known that the resistivity of the amorphous silicon varies depending upon the content of hydrogen or other impurities (N. Savvides, J. Appl. Phys., 56, 2789, 1984). If the content of hydrogen varies, for example, from 0% to 10%, the resistivity of the amorphous silicon varies by six orders of magnitude and it is, therefore, necessary that, in order to satisfy the aforementioned characteristic (a), the thickness of the film involved be varied from a few nm to several 1000 nm. In a practical process, there occurs a deposit of an insulating interlayer (SiO.sub.2) at low temperature and, in addition, hydrogen is incorporated into the amorphous silicon at a later step, such as a sintering step, but the amount of hydrogen involved is difficult to control. Therefore, it has been much more difficult to form a stabler antifuse element against the characteristic (a) above than to use the amorphous silicon.
If Al is used as the electrode from the standpoint of the process, Al is diffused into the antifuse material and, further, an Al hillock occurs at a later heating step, thus posing the problem that the hillock pierces through the antifuse material. If this is the case, then the antifuse element suffers an initial failure or a drop in breakdown voltage. In order to provide proper deposition of an amorphous silicon, the aspect ratio of the opening at an antifuse formation area is so designed as to be below 1/2. Even according to the present invention, however, it is unavoidable that an amorphous film becomes thinner at the edge of the opening. It is, therefore, not possible to expect much from this method. Further, in the real manufacture of an FPGA product, an antifuse process is incorporated into a conventional gate array process. From this viewpoint, the prior art device requires ample room for improvement. In an arrangement of an antifuse element provided between the Al connection layers and its manufacturing process, problems arise when this element or process is compatibly applied to the conventional process for practical application to an FPGA or when a stabler element is to be manufactured. To be specific, tasks to be solved are to obtain an antifuse film stable to the process, to prevent occurrence of a hillock in the Al connection layer, to obtain a structure whereby an antifuse film can be properly deposited, to provide vias from a standpoint of process integration, etc.